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Inter-Integrated Circuit
9.3.2.2
I 2 C Frequency Divider register
7
6
5
4
3
2
1
0
Read
Write
MULT
ICR
Reset
0
0
0
0
0
0
0
0
= Unimplemented or reserved
Figure 9-3. I 2 C Frequency Divider register (IICF)
Table 9-3. I 2 C Frequency Divider register (IICF) field descriptions
Bit(s)
7–6
Field
MULT
Description
I 2 C
Multiplier Factor
The MULT bits define the multiplier factor mul.
This factor is used along with the SCL divider to generate the I 2 C baud rate. The multiplier factor mul as
defined by the MULT bits is provided below.
00 mul = 01
01 mul = 02
10 mul = 04
11 Reserved
I 2 C Clock Rate
The ICR bits are used to prescale the bus clock for bit rate selection.
These bits and the MULT bits are used to determine the IIC baud rate, the SDA hold time, the SCL Start
hold time and the SCL Stop hold time. Table 9-6 provides the SCL divider and hold values for corresponding
values of the ICR.
The SCL divider multiplied by multiplier factor mul is used to generate IIC baud rate.
I 2 C Baud Rate = Bus Speed (Hz)/(mul × SCL Divider)
Eqn. 9-1
SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data).
5–0
ICR
SDA Hold Time = Bus Period (s) × mul × SDA Hold Value
Eqn. 9-2
SCL start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to
the falling edge of SCL (IIC clock).
SCL Start Hold Time = Bus Period (s) × mul × SCL Start Hold Value
SCL stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA
SDA ( IIC data) while SCL is high (Stop condition).
SCL Stop Hold Time = Bus Period (s) × mul × SCL Stop Hold Value
Eqn. 9-3
Eqn. 9-4
For example, if the bus speed is 8 MHz, Table 9-4 shows the possible hold time values with different ICR
and MULT selections to achieve an I 2 C baud rate of 100 kbps.
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
158
Freescale Semiconductor, Inc.
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